Collection
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Microsoft Windows NT
Operating System
Company: | Microsoft |
derives from: | Microsoft MS-Windows |
os runs on: | HP Evo D530 |
os runs on: | HP BL480c Blade Server |
os runs on: | HP BL460c Blade Server |
os runs on: | DEC Personal Workstation 600a |
os runs on: | DEC Multia VX40 |
os runs on: | DEC Multia VX41 |
os runs on: | DEC Multia VX51 |
os runs on: | Compaq Evo D510 |
os runs on: | Siemens RM 200 C |
- Details
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Sun Ultra 60
System
Company: | Sun (Sun Microsystems) |
Bus: | PCI, UPA |
Introduction: | 1997 |
Maximum memory size: | 2GB |
Maximum number of CPUs: | 2 |
uses architecture: | SPARC (Scalable Processor Architecture) |
runs os: | Sun SunOS/Solaris |
can contain: | Sun UltraSPARC-II |
System class: | Workstation |
Contains: | 2 * Sun UltraSPARC-II |
- Details
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DEC Personal Workstation 600a
System
Company: | DEC (Digital Equipment Corporation) |
Bus: | PCI |
Introduction: | 1997 |
Maximum number of CPUs: | 1 |
uses architecture: | Alpha |
runs os: | Microsoft Windows NT |
can contain: | DEC 21164A (EV56) |
System class: | Workstation |
Contains: | DEC 21164A (EV56) |
- Details
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- Details
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DEC 21264 (EV6)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1996 |
Technology: | 350nm CMOS, 15.2 million transistors |
Word size: | 64 |
can be contained in: | DEC AlphaServer DS20 |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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DEC 21264A (EV67)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1999 |
Technology: | 250nm CMOS, 15.2 million transistors |
Word size: | 64 |
can be contained in: | DEC AlphaServer DS10 |
can be contained in: | Compaq AlphaServer DS20E |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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DEC 21264C (EV68CB)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1999 |
Technology: | 180nm CMOS, 15.5 million transistors |
Word size: | 64 |
can be contained in: | HP AlphaServer DS15 |
can be contained in: | HP AlphaServer DS20L |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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DG Nova 4
System
Company: | DG (Data General) |
Introduction: | 1978 |
Maximum number of CPUs: | 1 |
uses architecture: | Nova |
runs os: | DG RDOS |
can contain: | DG Nova 4 |
System class: | Minicomputer |
Contains: | DG Nova 4 |
- Details
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DEC 21064A (EV45)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1993 |
Technology: | 500nm CMOS, 2.8 million transistors |
Word size: | 64 |
can be contained in: | DEC AlphaStation 250 |
can be contained in: | DEC AlphaStation 255 |
can be contained in: | DEC AlphaServer 400 |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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DEC 21064 (EV4)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1992 |
Technology: | 750nm CMOS, 1.68 million transistors |
Word size: | 64 |
can be contained in: | DEC 3000 AXP 800 |
can be contained in: | DEC 4000 AXP |
can be contained in: | DEC AlphaServer 2100A |
can be contained in: | DEC EB64+ |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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DEC 21164 (EV5)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1995 |
Technology: | 500nm CMOS, 9.3 million transistors |
Word size: | 64 |
can be contained in: | DEC AlphaServer 8200 |
can be contained in: | DEC AlphaServer 1000A |
can be contained in: | DEC AlphaServer 1200 |
can be contained in: | DEC AlphaServer 1000 |
can be contained in: | DEC Server 5000 Model 5305 |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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IBM RS64-III
CPU Chip
Company: | IBM (International Business Machines) |
Endianness: | bi |
Introduction: | 1999 |
Technology: | 220nm CMOS, 34 million transistors |
Word size: | 64/32 |
can be contained in: | IBM RS/6000 7026-H80 |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | POWER (Performance Optimization With Enhanced RISC) |
- Details
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EPIC (Explicitly Parallel Instruction Set Computer)
CPU Architecture Class
cpu architecture in this class: | IA64 (Itanium) |
- Details
Read more: EPIC (Explicitly Parallel Instruction Set Computer)
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Nova
CPU Architecture
Endianness: | big |
Word size: | 16 |
architecture used in: | DG Nova 4 |
architecture used in: | ROLM 1666B |
cpu using this architecture: | DG Nova 4 |
cpu architecture class: | Load/Store Architecture |
- Details
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DG Nova 4
CPU Chip
Company: | DG (Data General) |
Endianness: | big |
Technology: | 4 AMD2901 bitslices |
Word size: | 16 |
can be contained in: | DG Nova 4 |
cpu architecture class: | Load/Store Architecture |
cpu architecture: | Nova |
- Details
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DEC 21164A (EV56)
CPU Chip
Company: | DEC (Digital Equipment Corporation) |
Endianness: | little |
Introduction: | 1996 |
Technology: | 350nm CMOS, 9.7 million transistors |
Word size: | 64 |
can be contained in: | DEC Personal Workstation 600a |
can be contained in: | DEC AlphaServer 1000A |
can be contained in: | DEC AlphaServer 1200 |
can be contained in: | DEC AlphaServer 4100 |
can be contained in: | DEC AlphaServer 800 |
can be contained in: | DEC Server 3000 Model 3300 |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
cpu architecture: | Alpha |
- Details
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Alpha
CPU Architecture
Endianness: | little |
Word size: | 64 |
architecture used in: | Tadpole ALPHAbook 1 |
architecture used in: | HP AlphaServer ES47 |
architecture used in: | HP AlphaServer DS15 |
architecture used in: | HP AlphaServer DS20L |
architecture used in: | DEC AlphaServer 8200 |
architecture used in: | DEC Personal Workstation 600a |
architecture used in: | DEC AlphaStation 200 |
architecture used in: | DEC AlphaStation 250 |
architecture used in: | DEC AlphaStation 255 |
architecture used in: | DEC 3000 AXP 300X |
architecture used in: | DEC 3000 AXP 400/600/700 |
architecture used in: | DEC 3000 AXP 800 |
architecture used in: | DEC Multia VX40 |
architecture used in: | DEC Multia VX41 |
architecture used in: | DEC DMCC |
architecture used in: | DEC 4000 AXP |
architecture used in: | DEC AlphaServer DS10 |
architecture used in: | DEC AlphaServer DS20 |
architecture used in: | DEC AlphaServer ES40 |
architecture used in: | DEC AlphaServer 1000A |
architecture used in: | DEC AlphaServer 1200 |
architecture used in: | DEC AlphaServer 2100A |
architecture used in: | DEC AlphaServer 400 |
architecture used in: | DEC AlphaServer 4000 |
architecture used in: | DEC AlphaServer 4100 |
architecture used in: | DEC AlphaServer 500 |
architecture used in: | DEC AlphaServer 800 |
architecture used in: | DEC AlphaServer 1000 |
architecture used in: | DEC EB64+ |
architecture used in: | DEC Server 3000 Model 3300 |
architecture used in: | DEC Server 5000 Model 5305 |
architecture used in: | Compaq AlphaServer DS20E |
cpu using this architecture: | DEC 21164A (EV56) |
cpu using this architecture: | DEC 21064A (EV45) |
cpu using this architecture: | DEC 21064 (EV4) |
cpu using this architecture: | DEC 21164 (EV5) |
cpu using this architecture: | DEC 21264 (EV6) |
cpu using this architecture: | DEC 21264A (EV67) |
cpu using this architecture: | DEC 21264C (EV68CB) |
cpu using this architecture: | DEC 21066 (LCA4) |
cpu using this architecture: | DEC 21364 (EV7) |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
- Details
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POWER (Performance Optimization With Enhanced RISC)
CPU Architecture
Endianness: | bi |
Word size: | 64/32 |
architecture used in: | IBM RS/6000 7006-42T |
architecture used in: | IBM 6151 RT |
architecture used in: | IBM AS/400 9406-720 |
architecture used in: | IBM RS/6000 7026-H80 |
architecture used in: | IBM RS/6000 7026-6M1 |
cpu using this architecture: | IBM RS64-III |
cpu using this architecture: | IBM ROMP |
cpu using this architecture: | IBM PowerPC 604 |
cpu architecture class: | RISC (Reduced Instruction Set Computer) |
- Details
Read more: POWER (Performance Optimization With Enhanced RISC)