Write a commentMIPS (Microprocessor without Interlocked Pipeline Stages)
CPU Architecture
| Endianness: | bi |
| Word size: | 32/64 |
| can be contained in: | SGI Onyx2 Deskside |
| can be contained in: | SGI Indigo2 |
| can be contained in: | SGI Indy |
| architecture used in: | SGI Onyx2 Deskside |
| architecture used in: | SGI Fuel |
| architecture used in: | SGI Indigo2 |
| architecture used in: | SGI Indy |
| architecture used in: | SGI Iris Indigo |
| architecture used in: | SGI Personal Iris 4D/35 |
| architecture used in: | DEC DECstation 2100 |
| architecture used in: | DEC DECstation 3100 |
| architecture used in: | DEC DECstation 5000/240 |
| architecture used in: | DEC Personal DECstation 5000/25 |
| architecture used in: | DEC DECstation 5000/200 |
| architecture used in: | DEC DECstation 5000/133 |
| architecture used in: | DEC DECstation 5000 |
| architecture used in: | DEC DECsystem 5400 |
| architecture used in: | DEC DECsystem 5000/200 |
| architecture used in: | DEC DECsystem 5500 |
| architecture used in: | Siemens RM 200 C |
| cpu using this architecture: | MTI R12000 |
| cpu using this architecture: | MTI R3000 |
| cpu using this architecture: | MTI R4400 |
| cpu using this architecture: | MTI R10000 |
| cpu using this architecture: | QED R4600 |
| cpu using this architecture: | QED R4700 |
| cpu architecture class: | RISC (Reduced Instruction Set Computer) |